Cesium Modulation in Cu(In, Ga)(S, Se)2 Solar Cells: Comprehensive Analysis on Interface, Surface, and Grain Boundary

Cesium (Cs) incorporation and sulfurization on copper indium gallium selenide solar cells are the keys to improving the device quality. In this study, we explore the impact of Cs modulation on sulfur-containing Cu(In, Ga)(S, Se)2 (CIGSSe) absorbers, resulting in a performance increase of over 2%, reaching 18.11%. The improvement stems from a widened surface bandgap, grain boundary (GB) passivation, and a moderate injection blocking layer. The surface bandgap widens from 1.44 to 2.63 eV after Cs incorporation, confirmed by ultraviolet photoelectron spectroscopy (UPS) and low-energy inverse photoemission spectroscopy (LEIPS) analysis. Cs presence and S depletion in GBs suggest a new phase that might mitigate carrier recombination. Heightened Cs incorporation introduces interface issues, including an augmented injection blocking layer and interface defects. Our study offers insights into interface challenges and GB engineering strategies in Cs-treated CIGSSe solar cells, illuminating the multifaceted impact of heavy alkali metal ion Cs in CIGS-based photovoltaics.

Equation S 4  An increase in the NCV-NDL values at zero bias indicates an increment in the number of interface traps present at the CIGSSe/CdS p-n junction.Our data suggests that the Cs incorporation may lead to an increase in interfacial defects with a higher level of Cs incorporation.This elucidates that the performance degradation on Overdose_Cs-CIGSSe is not solely due to the lower free carrier concentration but also due to the emergence of severe interfacial defects at the junction.forward bias, the potential across the p-n junction decreases, and the defect states located in the near interface can be probed by the Fermi level of p-CIGS under the one-side approximation 29 .As a result, the emergence of an extra capacitance step, observed as the applied forward voltage increases, is likely attributed to the presence of additional defect states near the p-n interface.However, if the forward bias is higher than the device's VOC, the additional step may disappear at the hightemperature region due to the pronounced diffusion capacitance (see Figure S1 (d)).Thus, an excessive forward bias could bring considerable diffusion capacitance and destroy the capacitance-frequency profile.

Figure S 9 .
Figure S 9. The (a) J-V and (b) EQE characteristic curves of Low_Cs-CIGSSe devices with anti-reflection coating, showcasing the champion cell with a device area of 0.27 cm 2 .

Figure S 10 .
Figure S 10. UPS and LEIPS measurement for front interface band gap of Low_Cs-CIGSSe absorber.

Table S 2
. Correlation summary between carrier concentration, as obtained from CV and DLCP measurements, and the corresponding increase in VOC following Cs incorporation in CIGSSe.

Table S 3
. Atomic percent of CIGSSe at the front surface obtained from XPS measurement and its corresponding calculated bandgap.